CMOS image sensors are increasingly being used as low cost imaging devices. A CMOS image sensor circuit includes a focal plane array of pixel cells, each one of the cells includes a photogate, photoconductor, or photodiode having an associated charge accumulation region within a substrate for accumulating photo-generated charge. Each pixel cell may include a transistor for transferring charge from the charge accumulation region to a sensing node, and a transistor, for resetting the sensing node to a predetermined charge level prior to charge transference. The pixel cell may also include a source follower transistor for receiving and amplifying charge from the sensing node and an access transistor for controlling the readout of the cell contents from the source follower transistor.
In a CMOS image sensor, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) transfer of charge to the sensing node accompanied by charge amplification; (4) resetting the sensing node to a known state before the transfer of charge to it; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge from the sensing node.
CMOS image sensors of the type discussed above are generally known as discussed, for example, in Nixon et al., “256×256 CMOS Active Pixel Sensor Camera-on-a-Chip,” IEEE Journal of Solid-State Circuits, Vol. 31(12), pp. 2046-2050 (1996); and Mendis et al., “CMOS Active Pixel Image Sensors,” IEEE Transactions on Electron Devices, Vol. 41(3), pp. 452-453 (1994). See also U.S. Pat. Nos. 6,177,333 and 6,204,524, which describe operation of conventional CMOS image sensors and are assigned to Micron Technology, Inc., the contents of which are incorporated herein by reference.
A schematic diagram of a conventional CMOS pixel cell 10 is shown in FIG. 1A. FIG. 1B is a top plan view of the conventional pixel cell 10. The illustrated CMOS pixel cell 10 is a four transistor (4T) cell. The CMOS pixel cell 10 generally comprises a photo-conversion device 21 for generating and collecting charge generated by light incident on the pixel cell 10, and a transfer transistor 24 for transferring photoelectric charges from the photo-conversion device 21 to a sensing node, typically a floating diffusion region 15. The floating diffusion region 15 is electrically connected to the gate of an output source follower transistor 26, typically by a metal line 20 and contacts 23. The pixel cell 10 also includes a reset transistor 25 for resetting the floating diffusion region 15 to a predetermined voltage; and a row select transistor 27 for outputting signals from the source follower transistor 26 to an output terminal in response to an address signal. As shown in FIG. 1B, the reset transistor 25, source follower transistor 26, and row select transistor 27 each include a gate stack 29 and respective source/drain regions 22.
FIG. 1C is a cross-sectional view of a portion of the pixel cell 10 along the line 1C-1C′. As shown in FIG. 1C, the exemplary CMOS pixel cell 10 has a pinned photodiode as the photo-conversion device 21. The photodiode 21 uses a p-n-p construction comprising a p-type surface layer 14 and an n-type photodiode region 16 within a p-type active layer 11. The photodiode 21 is adjacent to and partially underneath the transfer transistor 24. The transfer transistor 24, as well as the other transistors 25, 26, 27, includes a gate stack 29. The gate stack 29 typically includes a gate dielectric layer 17, a gate electrode 18, a dielectric layer 19 and sidewall spacers 13. Typically, the gate electrode 18 is a planar layer.
In the CMOS pixel cell 10 depicted in FIGS. 1A-1C, electrons are generated by light incident on the photo-conversion device 21 and are stored in the n-type photodiode region 16. These charges are transferred to the floating diffusion region 15 by the transfer transistor 24 when the transfer transistor 24 is activated. The source follower transistor 26 produces an output signal from the transferred charges. A maximum output signal is proportional to the number of electrons extracted from the n-type photodiode region 16. The row select transistor 27 is operational to allow the source follower transistor 26 to output a reset signal Vrst when the reset transistor 25 resets the floating diffusion region 15, and a light received signal Vphoto when charge is transferred from the photodiode region 16 to the floating diffusion region 15.
When pixel cells 10 are scaled to smaller sizes (e.g., below 2 μm2), conventional transfer transistors 24 having planar gate electrodes 18 have difficulty fully transferring charge from the photo-conversion device 21. Factors reducing the charge transfer efficiency include the presence of potential barrier/wells near the transfer gate stack 29 region in the substrate 11, the threshold voltage of the transfer gate stack 29, and the reduced width of the transfer gate electrode 18. When pixel cells 10 are scaled, the transfer gate electrode 18 width and length, and oxide layer 17 thickness are correspondingly reduced. Unfortunately, at a particular operating voltage Vcc, reducing the gate width leads to poor charge transfer efficiency, while reducing the gate length leads to short-channel effects. Reducing the gate dielectric thickness, however, improves the gate overdrive, but care must be taken to maintain the gate dielectric 17 integrity.
It is desirable, therefore, to have an improved pixel cell that could be scaled to smaller sizes while maintaining efficient charge transfer.